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ASIC/FGPA Verification Engineer
Austin, TX
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ASIC/FGPA Verification Engineer

Location: Hybrid, Austin, TX (3 days onsite each week)


An innovative leader in cybersecurity solutions is growing its next-generation silicon and FPGA programs and is looking for an ASIC/FPGA Verification Engineer to help validate and optimize high-performance hardware systems for accuracy, reliability, and durability.

In the role of ASIC/FPGA Verification Engineer, you will lead the development and implementation of comprehensive verification plans for complex, large-scale FPGA architectures. You will develop structured verification environments, guide validation efforts through completion, and partner with cross-functional engineering teams to support successful hardware launches.


Key Responsibilities

  • Create and support verification environments for advanced FPGA platforms designed to handle intensive data operations.
  • Architect reusable, modular verification components using advanced SystemVerilog and object-oriented programming techniques.
  • Create directed and constrained random stimulus to validate functional correctness and corner case behavior.
  • Implement drivers, monitors, scoreboards, assertions, and coverage models to ensure comprehensive validation.
  • Evaluate coverage data to inform validation progress and strengthen overall design quality.
  • Debug failing simulations, recreate issues, and perform root cause analysis across RTL and verification environments.
  • Partner with design engineers to define and refine verification plans, test strategies, and quality benchmarks.
  • Continuously enhance verification methodology, tooling, automation, and reporting processes.
  • Leverage modern scripting and automation tools to streamline regression and productivity workflows.


Required Qualifications

  • Bachelor’s degree in electrical engineering, Computer Engineering, Computer Science, or a related discipline.
  • At least seven years of experience validating FPGA or ASIC designs utilizing UVM frameworks.
  • Extensive proficiency in SystemVerilog, object-oriented design principles, and building adaptable verification infrastructures.
  • Hands-on experience establishing UVM-based verification structures and guiding comprehensive test planning initiatives.
  • Hands on experience with industry standard simulation and debug tools.
  • Strong analytical and problem-solving skills with the ability to work effectively in cross functional teams.
  • Exposure to scripting tools that support automation and improve overall testing efficiency.


Preferred Experience

  • Working knowledge of industry-standard high-bandwidth communication protocols and comparable interface technologies.
  • Exposure to networking protocols including Ethernet, IP, TCP, or UDP.
  • Experience integrating third party verification IP into UVM environments.
  • Background supporting AI or machine learning related hardware acceleration is a plus.


Benefits

The organization offers a competitive compensation package, performance-based incentives, comprehensive medical, dental, and vision coverage, retirement plan with company match, paid time off, and professional development support.


About Blue Signal:  

Blue Signal is an award-winning, executive search firm specializing in various specialties. Our recruiters have a proven track record of placing top-tier talent across industry verticals, with deep expertise in numerous professional services. Learn more at bit.ly/46Gs4yS 


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